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RF9957
7
Typical Applications
* CDMA/FM Cellular Systems * CDMA PCS Systems * Wireless Local Loop Systems * Spread-Spectrum Cordless Phones * High Speed Data Modems * General Purpose Digital Receivers
CDMA/FM RECEIVE AGC AND DEMODULATOR
Product Description
The RF9957 is an integrated complete IF AGC amplifier and Quadrature Demodulator designed for the receive section of dual-mode CDMA/FM cellular and PCS applications. It is designed to amplify received IF signals, while providing 100dB of gain control range, and demodulate to baseband I and Q signals. Noise Figure, IP3, and other specifications are designed to be compatible with the IS98 and J-STD-018 Interim Standard for CDMA cellular communications. The IC is manufactured on an advanced 15GHz FT Silicon Bipolar process, and is packaged in a standard miniature 24-lead plastic SSOP package.
0.157 0.150
0.0098 0.0040
1
0.344 0.337
0.012 0.008
0.025 0.0688 0.0532
7
QUADRATURE DEMODULATORS
0.2440 0.2284 8MAX 0MIN
0.050 0.016
0.0098 0.0075
Optimum Technology Matching(R) Applied
u
Package Style: SSOP-24
Si BJT Si Bi-CMOS
GaAs HBT SiGe HBT
GaAs MESFET Si CMOS
Features
* Supports Dual Mode Operation (CDMA and FM)
FL+
GC
23
19
* Digitally Controlled Power Down Mode * 2.7V to 3.3V Operation
16 Q OUT+ 15 Q OUT-
CDMA IN+ 4 CDMA IN- 5 IN SEL 14 FM IN+ 8 FM IN- 9 Input Select
Gain Control
* Quadrature LO Divider * IF AGC Amp with 100dB Gain Control
Quad. /2
13 LO+ 12 LO21 I OUT+
Band Gap Reference
22 I OUT-
Ordering Information
24 PD 18 FL-
10 BG OUT
RF9957 RF9957 PCBA
CDMA/FM Receive AGC and Demodulator Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev C11 010622
7-27
RF9957
Absolute Maximum Ratings Parameter
Supply Voltage Power Down Voltage (VPD) Input RF Power Ambient Operating Temperature Storage Temperature
Rating
-0.5 to +5 -0.5 to VCC +0.7 +3 -40 to +85 -40 to +150
Unit
VDC VDC dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall (Cascaded)
Maximum Gain Minimum Gain Gain Variation vs. VCC and T Input IP3
Specification Min. Typ. Max.
Unit
Condition
T=25 C, VCC =3.0V, ZLOAD =5k, LO=170MHz @400mVPP, IF Freq=85MHz, ZS =500 (CDMA), ZS =850 (FM) VGC =2.5V, FM or CDMA Input, Balanced VGC =0.5V, FM or CDMA Input, Balanced VCC =2.7V to 3.3V and T=-30C to +85C VGC =2.5V, Maximum Gain Gain = 35 dB, PIN=-61dBm VGC =0.5V, Minimum Gain VGC =2.5V, Maximum Gain VGC =0.5V, Minimum Gain FM or CDMA, Balanced FM or CDMA, Single Ended
+45 -3 -39
+50 -55 -50 -36 -4 5 70 50 to 250 2400 1200 0 to 50 0.1 1 2.0 5 100 to 500 60 to 600 800 400 3.0 14.5 12.5
-50 +3
7
QUADRATURE DEMODULATORS
Noise Figure IF Input Frequency Range IF Input Impedance I/Q Frequency Range I/Q Amplitude Balance I/Q Phase Balance Max I/Q Output Voltage I/Q DC Output I/Q DC Offset LO Input Frequency Range LO Input Level LO Input Impedance
2040 1020
2760 1380 0.5 5
500 20
680 340 2.7
920 460 3.3 18 16 10
dB dB dB dBm dBm dBm dB dB MHz MHz dB deg mVPP VDC mVDC MHz mVPP VDC mA mA A
Balanced, maximum output level Common Mode I OUT+ to I OUT-; Q OUT+ to Q OUTBalanced Balanced Single Ended
Power Supply
Supply Voltage Current Consumption CDMA Mode FM Mode Sleep Mode (PD 0.5V)
7-28
Rev C11 010622
RF9957
Pin 1 Function VCC1 Description
Supply voltage for the LO flip-flop divider and limiting amp. This pin may be connected in parallel with pins 2 and 3. It should be bypassed by a 10nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. Supply voltage for the bandgap, gain control bias circuitry, and AGC stages 2, 3, and 4. This pin may be connected in parallel with pins 1 and 3. It should be bypassed by a 10nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. Supply voltage for the FM and CDMA AGC input stages. This pin may be connected in parallel with pins 1 and 2. It should be bypassed by a 10nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. CDMA Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with a DC level present. For single-ended input operation, one pin is used as an input and the other CDMA input is AC coupled to ground. The balanced input impedance is 2.4k, while the single-ended input impedance is 1.2k.
CDMA IN+
Interface Schematic
2
VCC2
3
VCC3
4
CDMA IN+
BIAS
BIAS
1200
1200
CDMA IN-
7
QUADRATURE DEMODULATORS
5 6 7 8
CDMA INGND GND FM IN+
Same as pin 4, except complementary input. Ground connection. Keep traces physically short and connect immediately to ground plane for best performance. Same as pin 6. FM Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. For single-ended input operation, one pin is used as an input and the other FM input is AC coupled to ground. The balanced input impedance is 2.4k, while the single-ended input impedance is 1.2k.
See pin 4.
BIAS
BIAS
1200
1200
FM IN+
FM IN-
9 10
FM INBG OUT
Same as pin 8, except complementary input. Bandgap Voltage Reference. This voltage, constant over temperature and supply variation, is used to bias internal circuits. A 10nF external bypass capacitor is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. AGC decoupling pin. An external bypass capacitor of 10nF capacitor is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. LO Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. For single-ended input operation, one pin is used as an input and the other LO input is AC coupled to ground. The frequency of the signal applied to these pins is internally divided by a factor of 2, hence the carrier frequency for the modulator becomes one half of the applied frequency. The singleended input impedance is 400 (balanced is 800). The LO input may be driven single-ended but balanced provides optimum gain and phase balance. Same as pin 12, except complementary input.
See pin 8.
11
DEC
12
LO-
BIAS
BIAS
400
400
LO-
LO+
13
LO+
See pin 12.
Rev C11 010622
7-29
RF9957
Pin 14 Function IN SEL Description
Selects between CDMA and FM mode. This is a digitally controlled input. A logic "high" (VCC-0.7VDC) selects CDMA mode. A logic "low" (<0.5VDC) selects FM mode. In FM mode, ONLY the I mixer is active. There is no Q output in FM mode. The impedance on this pin is 30k.
IN SEL
Interface Schematic
BIAS
60 k 60 k
15
Q OUT-
Balanced Baseband Output of Q Mixer. This pin is internally DC biased and should be DC blocked externally. This output is active in CDMA mode, but is NOT active in FM mode. The output can be used in a single-ended configuration by leaving one of the two pins unconnected, however half the output voltage will be lost. Each pin should be loaded with 2.5k. The balanced load should be 5k. The single-ended output impedance is 1k, while the balanced output impedance is 2k.
VCC
VCC
1 k
1 k Q OUT+ Q OUT-
16 17 18
Q OUT+ GND FL-
Same as pin 15, except complementary output. Same as pin 6. Balanced AGC Output/Demod Input. This balanced node is pinned out to allow shunt filtering of the AGC output signal as it enters the demodulator. The basic configuration of the filter should consist of a shunt inductor and shunt capacitor, both connected to the power supply, as the internal circuitry requires this power supply connection through the inductor to operate.
See pin 15.
FL- FL+
7
QUADRATURE DEMODULATORS
VCC2
VCC2
VCC1
VCC1
1.2 k
1.2 k
19 20 21
FL+ GND I OUT+
Same as pin 18, except complementary. Same as pin 6. Balanced Baseband Output of I Mixer. This pin is internally DC biased and should be DC blocked externally. This output is active in both CDMA and FM modes. The output can be used in a single-ended configuration by leaving one of the two pins unconnected, however half the output voltage will be lost. Each pin should be loaded with 2.5k. The balanced load should be 5k. The single-ended output impedance is 1k, while the balanced output impedance is 2k.
See pin 18.
VCC
VCC
1 k
1 k I OUT+ I OUT-
22 23
I OUTGC
Same as pin 21, except complementary output. Analog Gain Control for AGC Amplifiers. The valid control range is from 0.5 to 2.5VDC. These voltages are valid for ONLY a 37k source impedance. The gain range for the AGC is 95dB.
See pin 22.
BIAS
21 k
GC
40 k
7-30
Rev C11 010622
RF9957
Pin 24 Function PD Description
Power Down Control. When logic "high" (VCC-0.3V), all circuits are operating; when logic "low" (0.5V), all circuits are turned off. The input impedance of this pin is 10k.
10 k PD
Interface Schematic
Pin Out
VCC1 1 VCC2 2 VCC3 3 CDMA IN+ 4 CDMA IN- 5 GND 6 GND 7 FM IN+ 8 FM IN- 9 BG OUT 10 DEC 11 LO- 12 24 PD 23 GC 22 I OUT21 I OUT+ 20 GND 19 FL+ 18 FL17 GND 16 Q OUT+ 15 Q OUT14 IN SEL 13 LO+
7
QUADRATURE DEMODULATORS
Rev C11 010622
7-31
RF9957
Application Schematic
VCC 100 pF Power Down 1 10 nF 2 3 4 680 CDMA IN5 6 7 10 nF FM IN+ 8 10 nF 9 10 nF FM INQ OUT+ 16 100 nF 10 BG OUT 10 nF 11 DEC 1 nF 12 LOLO+ 13 LO IN IN SEL 14 1 nF 100 pF Input Select Q OUT- 15 Q OUTFM IN+ GND 17 100 nF Q OUT+ CDMA INGND GND GND 20 7 pF FL+ 19 7 pF FL- 18 390 nH 10 nF VCC VCC2 VCC3 CDMA IN+ GC 23 100 nF CDMA SAW Filter CDMA IN+ I OUT- 22 100 nF I OUT+ 21 390 nH I OUT+ I OUT10 nF VCC1 PD 24 37 k Gain Control
7
QUADRATURE DEMODULATORS
7-32
Rev C11 010622
RF9957
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
P1 P1-1 1 2 P1-3 3 PD GND VCC P2-3 P2-1 P2 1 2 3 GC GND IN SEL P3-3 P3-1 P3 1 2 3 +5 VDC GND -5 VDC R13 36 k P1-1 C26 100 nF P1-3 C2 10 F C5 13 pF T1 1 C6 13 pF L2 390 nH C8 9.1 pF L3 330 nH C4 10 nF L1 390 nH C7 20 pF R14 3 k C9 10 nF 9 C10 10 nF 10 BG OUT C11 10 nF 11 DEC J3 LO 50 strip T2 1 R2 270 C13 1 nF
9957400 Rev B
R15 1 k P2-1
C25 100 nF 1 C1 10 nF C3 10 nF R1 680 2 3 4 5 6 7 8 VCC1 VCC2 VCC3 CDMA IN+ CDMA INGND GND FM IN+ FM INPD 24 GC 23 I OUT- 22 I OUT+ 21 L4 390 nH GND 20 C20 6.8 pF FL+ 19 L5 390 nH FL- 18 C19 6.8 pF GND 17 Q OUT+ 16 Q OUT- 15 IN SEL 14 LO+ 13 C28 100 nF C29 100 nF R3 4.3 k R4 820 R5 1.6 k
3
C30 100 nF C31 100 nF
R9 820 R8 4.3 k
R12 1.6 k
3
C21 100 nF R11 51
C22 10 F P3-1 50 strip J5 I OUT P3-3
J1 CDMA
50 strip
CLC426/ 7 CL +V 6 + 2 - V4 U2
P1-3 C27 4.6 nF
R10 8.2 k
C23 100 nF
C24 10 F
J2 FM
50 strip
C17 100 nF R7 51
C18 10 F P3-1 50 strip J4 Q OUT P3-3
C12 1 nF 12 LO-
R6 8.2 k
C15 100 nF
C16 10 F
P2-3 C14 100 nF
Rev C11 010622
7-33
QUADRATURE DEMODULATORS
CLC426/ 7 CL +V 6 + 2 - V4 U1
7
RF9957
Evaluation Board Layout Board Size 3.025" x 3.025"
Board Size 0.031", Board Material FR-4
7
QUADRATURE DEMODULATORS
7-34
Rev C11 010622
RF9957
7
QUADRATURE DEMODULATORS
Rev C11 010622
7-35
RF9957
60 50 40
CDMA Cascade Conversion Gain versus Gain Control Voltage (VCC=3.0 V, 85 MHz)
60 50 40
FM Cascade Conversion Gain versus Gain Control Voltage (VCC=3.0V, 85MHz)
Cascade Conversion Gain (dB)
30 20 10 0 -10 -20 -30 -40 -50 -60 0.5 1 1.5 2 2.5 +25C -30C +85C
Cascade Conversion Gain (dB)
30 20 10 0 -10 -20 -30 -40 -50 -60 0.5 1 1.5 2 2.5 +25C -30C +85C
GC (V)
GC (V)
CDMA IIP3 versus Gain
FM IIP3 versus Gain
0
7
QUADRATURE DEMODULATORS
0
(VCC=3.0V, 85MHz)
(VCC=3.0V, 85MHz)
-10
-10
-20
-20
IIP3 (dBm)
-30
IIP3 (dBm)
-60 -40 -20 0 20 40 60
-30
-40
-40
-50
-50
-60
-60 -60 -40 -20 0 20 40 60
Gain (dB)
Gain (dB)
CDMA Noise Figure versus Gain
80
FM Noise Figure versus Gain
80
(VCC=3.0V, 85MHz)
(VCC=3.0V, 85MHz)
70
70
60
60
Noise Figure (dB)
50
Noise Figure (dB)
-60 -40 -20 0 20 40 60
50
40
40
30
30
20
20
10
10
0
0 -60 -40 -20 0 20 40 60
Gain (dB)
Gain (dB)
7-36
Rev C11 010622

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